Due to its relatively low resistance and cost, copper is finding increasing use as a conductive layer in the interconnect metallization structures of integrated circuits and other semiconductor devices. FIGS. 1A-1E show simplified cross-sectional views of conventional steps for fabricating a damascene interconnect structure utilizing copper metallization.
In FIG. 1A, an interlayer dielectric (ILD) 100 is formed over a first conducting layer 102 and then patterned to create opening 104. While opening 104 is generically shown in FIG. 1A as a via hole, in dual damascene approaches the opening can take the more complex form of a trench overlying a narrower via hole.
In FIG. 1B, a first barrier layer 106 is formed within opening 104 and over patterned ILD 100. Barrier layer 106 may be formed from a variety of materials, including but not limited to SiN, TiN, Ta, TaN, Ta/TaN, as well as the barrier low k (BLOK®) material manufactured by Applied Materials, Inc. of Santa Clara, Calif. The primary function of the barrier layer is to block diffusion of copper of the metallization structure. ILD 100 and barrier layer 106 may be formed by such techniques such as chemical vapor deposition, as performed by the PRODUCER® tool manufactured by Applied Materials, Inc. of Santa Clara, Calif.
In FIG. 1C, copper metal interconnect 108 is formed over first barrier layer 106, within opening 104 and over the top of ILD layer 100. The copper metal 108 may be formed by such techniques as electroplating, for example as is performed by the ELECTRA CU™ tool manufactured by Applied Materials, Inc. of Santa Clara, Calif.
In FIG. 1D, the wafer is removed from the electroplating device and transferred to a chemical mechanical polishing tool for removal of copper metal 108 and barrier layer 106 outside of the now-filled opening in ILD 100, resulting in the formation of conducting copper via structure 110. In FIG. 1E, the wafer is transferred from the chemical mechanical polishing module to a chemical vapor deposition (CVD) module for formation of second barrier layer 112 over copper via 110. The function of second barrier layer 112 to block any upward diffusion of copper metal from the via into successive dielectric layers of the interconnect structure.
The process sequence shown and described above in connection with FIGS. 1A-1E can be repeated to form additional metallization layers overlying and in contact with copper via 110.
The process flow just shown and described is somewhat simplified. For example, FIGS. 1CA-CC show detailed and enlarged views of the fabrication steps leading up to creation of the copper via shown in FIG. 1D. Specifically, removal of excess copper metal during the CMP step shown in FIG. 1C may be performed under oxidizing conditions. Thus, as shown in FIG. 1CB, at the conclusion of the CMP step and prior to formation of the second barrier layer, a thin copper oxide layer 114 typically overlies copper via plug 110. Formation of such a copper oxide layer is not necessarily the result of CMP performed under oxidizing conditions, and copper oxide may also result from exposing the processed wafer to air, as may occur during transfer of the wafer between different processing tools.
Because this copper oxide layer 114 is a dielectric material, it can degrade the conductive properties of the interconnected metallization Therefore, as shown in FIG. 1CC, the metallization layer may be exposed to a reactive ionized species from a plasma to remove the copper oxide prior to formation of the top barrier layer and additional portions of the interconnect structure. The oxide removal plasma may be generated in gases such as NH3 mixed with a carrier gas comprising N2. The oxide removal plasma may be generated remote from the chamber or generated within the chamber. This plasma exposure may take place in the same chamber in which the upper barrier layer is subsequently deposited. Methods and apparatuses for removing copper oxide are described in detail in U.S. Pat. No. 6,365,518, coassigned with the present invention and hereby incorporated by reference for all purposes.
Another detail not shown in the generalized FIGS. 1A-E is the potential undesirable formation of hillocks in the copper metallization layer. Hillock formation is shown and described in connection with FIGS. 1DA-1DC.
FIG. 1DA shows a cross-sectional view of the interconnect structure after removal of the CuO layer by plasma exposure following removal of the unwanted CuO layer. As shown in FIG. 1DB, hillocks 108a may undesirably grow out of the plane of the copper layer 108 prior to or during formation of the upper barrier layer. The growth and presence of hillocks 108a can create issues regarding performance of the interconnect structure, such as elevated electrical resistance and/or shorting.
Therefore, there is a need in the art for methods and apparatuses which reduce the incidence of hillock formation during the fabrication of copper metallization structures.